The testbench intends to facilitate the simulation tools by giving the required input in required order and taking the output of the simulation and checking it with the expected output.

If the testbench is sufficiently advanced, each and every signal in a design can be simulated and checked using the testbench.

But the complexity of the testbench increases with the complexity of the method of input required by the unit not with the complexity of the functionality of the design.

A good testbench can cover a wide range of inputs reducing the chances of the design failing in the real implementation.

For simplicity, the step by step guide uses verilog for the testbench development.

The testbench can be non-synthesizable and need not have any synergy with a hardware design.

This block is sequentially executed and usually contains the reset and starting the clock ticking.

An often used method is to read the inputs from the file and feeding them to the uut.

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Verilog Testbench Example